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5.13.5.1.5.1 System p
The instruction set for the PowerPC processor is given in the book at the following URL:
http://www.ibm.com/chips/techlib/techlib.nsf/techdocs/852569B20050FF778525699600682CC7/$file/booke
_rm.pdf
For each instruction, the description in the book lists whether it is available only in supervisor mode or not.
The following instructions are tested by the AMTU:
• TLBSYNC: TLB Synchronize
• MFSR: Move from Segment Register
• MFMSR: Move From Machine State Register
The expected outcome from attempting to execute these instructions is an ILLEGAL Instruction signal
(SIGILL – 4).
5.13.5.1.5.2 System z
The book entitled Principles of Operation is a handy reference for the System z architecture:
http://publibz.boulder.ibm.com/cgi-bin/bookmgr_OS390/BOOKS/DZ9AR006/CCONTENTS
The following privileged instructions are tested by this tool:
• PTLB: Purge TLB
• RRBE: Reset reference bit extended
• PALB: Purge ALB
• EPAR: Extract Primary ASN
• HSCH: Halt subchannel
• LPSW: Load PSW (To test the CPU control register).
The expected outcome from attempting to execute these instructions is an ILLEGAL Instruction signal
(SIGILL – 4).
5.13.5.1.5.3 System x
Section 4.9 from the Intel Architecture Software Developer's Manual Volume 3: System Programming book at
ftp://download.intel.com/design/PentiumII/manuals/24319202.pdf gives a list of privileged instructions
available for the x86 architecture.
This tool tests the following privileged instructions:
• HLT: halt the processor
• RDPMC: read performance-monitoring counter
• CLTS: Clear task-switched flag in register CR0.
• LIDT: Load Interrupt Descriptor Table Register
• LGDT: Load Global Descriptor Table Register
• LTR: Load Task Register
• LLDT: Load Local Descriptor Table Register
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