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IXD1110 Demo Board
14 Development Kit Manual
Document Number: 250807
Revision Number: 003
Revision Date: June 27, 2003
For more information on the HyperTerminal and GUI interfaces, please refer to the IXF1110
Software Help File.
4.1 CPU FPGA
The IXD1110 demo board has a Field Programmable Gate Array (FPGA) that allows the
Motorola* CPU, which requires a synchronous interface, to interoperate with the asynchronous
IXF1110 CPU interface.
For additional information regarding the IXF1110 CPU interface, refer to the IXF1110 Datasheet.
4.2 IXF1110 Register Modifications on Startup
The Motorola* CPU automatically modifies some of the IXF1110 registers on startup to put the
board in a 1000 Mbps evaluation mode. The following registers are modified from default settings
on startup:
• TX FIFO Highwater Mark Ports 0-9 are set to 0x00000BB8
• RX FIFO Errored Frame Drop Enable is set to 0x000003FF
• MAC Transfer Threshold Ports 0-9 are set to 0x000003E8
• Diverse Config Ports 0-9 are set to 0x0000112D
• LED Control is set to 0x00000003
For additional information on these registers, please refer to the IXF1110 Datasheet.