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Intel® Server Board S5000PAL / S5000XAL TPS Table of Contents
Revision 1.4
Intel order number: D31979-007
v
Table of Contents
1. Introduction ........................................................................................................................12
1.1 Chapter Outline......................................................................................................12
1.2 Server Board Use Disclaimer ................................................................................12
2. Product Overview...............................................................................................................13
2.1 Intel
®
Server Board S5000PAL / S5000XAL Feature Set......................................13
2.2 Server Board Layout..............................................................................................14
2.2.1 Connector and Component Locations ...................................................................15
2.2.2 Light Guided Diagnostic LED Locations ................................................................17
2.2.3 External I/O Connector Locations..........................................................................18
2.2.4 Server Board Mechanical Drawings ......................................................................19
3. Functional Architecture.....................................................................................................24
3.1 Intel
®
5000P and 5000X Memory Controller Hubs (MCH) .....................................25
3.1.1 System Bus Interface.............................................................................................25
3.1.2 Processor Support.................................................................................................25
3.1.3 Memory Sub-system..............................................................................................27
3.1.4 Snoop Filter (5000X MCH only).............................................................................33
3.2 ESB-2 IO Controller ...............................................................................................33
3.2.1 PCI Sub-system.....................................................................................................34
3.2.2 Serial ATA Support................................................................................................36
3.2.3 Parallel ATA (PATA) Support ................................................................................37
3.2.4 USB 2.0 Support....................................................................................................37
3.3 Video Support........................................................................................................37
3.4 Network Interface Controller (NIC) ........................................................................39
3.4.1 Intel
®
I/O Acceleration Technology ........................................................................39
3.4.2 MAC Address Definition.........................................................................................39
3.5 Super I/O ...............................................................................................................40
4. Platform Management........................................................................................................43
5. Connector / Header Locations and Pin-outs....................................................................44
5.1 Board Connector Information.................................................................................44
5.2 Power Connectors .................................................................................................45
5.3 System Management Headers ..............................................................................46
5.3.1 Intel
®
Remote Management Module (RMM) Connector ........................................46
5.3.2 Intel
®
RMM NIC Connector....................................................................................47
5.3.3 LCP/AUX IPMB Header.........................................................................................48
5.3.4 IPMB Header .........................................................................................................48