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Power and Environmental Specifications Intel
®
Server Board S5000PAL / S5000XAL TPS
Revision 1.4
Intel order number: D31979-007
74
8.2.8 Dynamic Loading
The output voltages shall remain within limits for the step loading and capacitive loading specified in the
table below. The load transient repetition rate shall be tested between 50 Hz and 5 kHz at duty cycles
ranging from 10%-90%. The load transient repetition rate is only a test specification. The Δ step load
may occur anywhere within the MIN load to the MAX load conditions.
Table 39. Transient Load Requirements
Output
Δ Step Load Size
(See note 2)
Load Slew Rate Test capacitive Load
+3.3V 5.0A
0.25 A/μsec 250 μF
+5V 6.0A
0.25 A/μsec 400 μF
12V1+12V2+12V3+12
V4
28.0A
0.25 A/μsec 2200 μF
1,2
+5VSB 0.5A
0.25 A/μsec 20 μF
Notes:
1) Step loads on each 12V output may happen simultaneously.
2) The +12V should be tested with 2200μF evenly split between the four +12V rails.
8.2.9 Capacitive Loading
The power supply shall be stable and meet all requirements with the following capacitive loading ranges.
Table 40. Capacitive Loading Conditions
Output MIN MAX Units
+3.3V 250 6,800
μF
+5V 400 4,700
μF
+12V1,2,3,4 500 each 11,000
μF
-12V 1 350
μF
+5VSB 20 350
μF
8.2.10 Closed-Loop Stability
The power supply shall be unconditionally stable under all line/load/transient load conditions including
capacitive load ranges. A minimum of: 45 degrees phase margin and -10dB-gain margin is required.
Closed-loop stability must be ensured at the maximum and minimum loads as applicable.
8.2.11 Common Mode Noise
The common mode noise on any output shall not exceed 350 mV pk-pk over the frequency band of 10Hz
to 30MHz.
1. The measurement shall be made across a 100 Ω resistor between each of the DC outputs,
including ground, at the DC power connector and chassis ground (power subsystem enclosure).
2. The test set-up shall use an FET probe such as Tektronix* model P6046 or equivalent.