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Crown Beach Board
User’s Manual 19
Document Number: 320264
• Two PS/2 ports.
Note: The two PS/2 ports are for a legacy keyboard and mouse. The keyboard plugs into the
bottom port and the mouse plugs into the top port.
• EMA support
• Wake/runtime SCI events
• Power sequencing control
2.5.10 EFI Firmware Hub (FWH)
A TSOP socket houses the flash device (ST Microelectronics P/N# M50FW080) that
stores the system EFI firmware. The EFI firmware can be programmed through a
Microsoft MS-DOS* or Windows*-based utility.
2.5.11 Trusted Platform Module (TPM) Header
Crown Beach implements a header at J9B4 to support TPM 1.2 specification compliant
devices. The same header can be used for legacy connections, allowing other SIO
solutions to provide floppy, COM, Parallel, and PS/2 functionality.
2.5.12 SD/SDIO/MMC
Crown Beach provides three ports with the following features:
• All ports are SD rev1.1 specification compliant and MMC rev4.0 specification
compliant.
• All ports operate to 48 MHz. Ports 0 and 1 support 4-bit operation. Port 2 supports
8-bit operation.
• Slot 2 is also routed (with stuffing options) to the PCI Express* Mini Card for
wireless solutions.
2.5.13 Clocks
The Crown Beach CRB uses a CK-540 clock solution. The BSEL [2:1] signals driven by
the processor are used by the CK-540 to configure the FSB frequency.
2.5.14 Real Time Clock
An on-board battery maintains power to the real time clock (RTC) when in a
mechanical off state (G3 state).