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Timers
16-Bit Timer Setup Examples
MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company
107
Panasonic
change any other operating modes during this step.
When TM4MD[1:0] = b’10’ (dur-
ing capture), TM4CA and
TM4CB become read-only regis-
ters. To write to TM4CA or
TM4CB, you must first set
TM4MD[1:0] = b’00’.
3. Set TM4NLD and TM4EN to 1. This starts the timer. Counting begins at the
start of the next cycle.
To enable timer 4 capture B interrupts:
Cancel all existing interrupt requests. Next, set the interrupt priority level in the
TM4CBLV[2:0] bits of the TM4CBICH register (levels 0 to 6), set the TM4BIE
bit to 1, and set the TM4BIR bit of TM4CBICL to 0. From this point on, an
interrupt request is generated whenever a timer 4 capture B event occurs.
■
To service the interrupts and calculate the signal width:
1. Run the interrupt service routine. The routine must determine the interrupt
group, then clear the interrupt request flag.
Ignore the flags when calculat-
ing the signal width, even when
TM3CA is the larger value.
2. Calculate the number of cycles the TM4IA signal stays high. Save the con-
tents of TM4CA and TM4CB to the data registers, then subtract the contents
of TM4CA from the contents of TM4CB. Since TM4LP is set to 0, the dif-
ference will be the correct value even if TM4CA is greater than TM4CB.
Timer 4 can input a single-phase capture signal. You must select up counting.
Timer 4 does not operate in STOP mode, when B
OSC
is off. If you use an external
clock, it must be synchronized to B
OSC
.
TM4CA captures the count on the rising edge of TM4IA, and TM4CB captures
the count on the falling edge of TM4IA. A timer 4 capture B interrupt occurs
when TM4CB captures the count, and the contents of TM4CA and TM4CB are
read during the interrupt service routine.
In the example timing chart shown in figure 4-36, x’000A’ – x’0007’ = x’0003’,
or 3 cycles. The calculation is correct even when TM4CA is the larger value. The
flags are ignored, so for instance, x’0003’ – x’FFFE’ = x’0005’.
■
Figure 4-36 Single-Phase Capture Input Timing (Timer 4)
TM4EN
TM4BC
B
OSC
/4
TM4CA
TM4CB
TM4IA
Interrupt
012340 5 6 7 8 9 A B C D E F 10 11 12
07
0A
A-7=3
B