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I/O Port Circuit Diagrams
Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual
272
Panasonic
Figure 11-22 P50/SYSCLK (Port 5)
P5PUP0
0: Pullup off
1: Pullup on
P5MD0
0: P50
1: SYSCLK
SYSCLK or
divided SYSCLK output
P5DIR0
0: Port input
1: Port output
P5OUT0
Pin
P5IN0
0: Port low output
1: Port high output
0
1
M
U
X
P50/SYSCLK