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I/O Port Circuit Diagrams
Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual
264
Panasonic
Figure 11-13 P02/SCL1 (Port 0) and P61/SCL0 (Port 6)
P0PUP2
0: Pullup off
1: Pullup on
0: Pullup off
1: Pullup on
P0MD2
0: P02
1: SCL1
P0DIR2
0: Port input
1: Port output
P0OUT2
SCL output
P0IN2
P6IN1
SCL input
0: Port low output
1: Port high output
I2CSEL1
I2CSEL0
Pin
M
0
1
U
X
Schmidt trigger
Schmidt trigger
P02/
SCL1
P6PUP1
P6MD1
0: P61
1: SCL0
P6DIR1
0: Port input
1: Port output
P6OUT1
0: Port low output
1: Port high output
Pin
M
0
1
U
X
P61/
SCL0