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Interrupts
Description
MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company
39
Panasonic
Figure 2-3 Interrupt Servicing Time
Table 2-2 Handler Preprocessing
Sequence Assembler Bytes Cycles
Push registers add -8,A3
mov A0,(A3)
movx D0,(4,A3)
2
2
3
1
2
3
Interrupt ACK mov (FC0E),D0 31
Generate header address
for interrupt service routine
mov BASE,A0
mov (D0,A0),A0
3
2
1
2
Branch jsr (A0) 25
To tal 1 7 1 5
Table 2-3 Handler Postprocessing
Sequence Assembler Bytes Cycles
Pop registers mov (A3),A0
movx (4,A3),D0
add 8,A3
2
3
2
2
3
1
To tal 7 6
Program
Interrupt
Max. 6 cycles
Interrupt hardware processing
(9 cycles)
Handler
(preprocessing)
Interrupt service
routine
Handler
(postprocessing)
Address 80008
jsr (5 cycles)
rts (5 cycles)
Registers popped
rti (7 cycles)
The interrupt request is
deleted in the header
(Included in the cycle
count shown to the left.)