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I
2
C Bus Controller
I
2
C Interface Setup Examples
Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual
300
Panasonic
13.6 I
2
C Interface Setup Examples
13.6.1 Setting Up a Transition from Master Transmitter to Mas-
ter Receiver
This example demonstrates how to set up a data transfer when changing from
master transmitter to master receiver. Figure 13-7 shows an example waveform.
13.6.1.1Pre-configuring
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To set up the I/O port:
Set port control register 0 (PCNT0; x’00FF90’) to x’0100’ (enabling the SDA0
and SCL0 pins) and set the port 6 output mode register (P6MD; x’00FFFC’) to
x’0003’ (selecting the SDA0 and SCL0 functions).
■
To enable I
2
C interrupts:
Set the I
2
C interrupt control register pair (I2C0ICH and I2C0ICL; x’00FC9C’) to
x’0100’.
■
To set up the I
2
C registers:
1. Set the I2CCLK register (x’007E46’) to x’0041’, selecting a clock frequency
of 80 kHz.
2. Set the I2CDTRM register (x'007E40') to x'05FD'. This sets STA to 1, STP
to 0, and ACK to 0. Bits 7 to 1 of the transmission data setting (x'FD') indi-
cate the address (b'1111110') of the slave device from which the microcon-
troller will request the data, and bit 0 indicates the read/write setting (bit 0 =
1 = read).
13.6.1.2Setting Up the First Interrupt
When an ACK = 0 signal returns from the slave device, the I
2
C bus controller
generates an interrupt. At this point, implement the following settings:
■
To set up the interrupt:
Set the I2C0ICH and I2C0ICL register pair (x’00FC9C’) to x’0100’. This
enables I
2
C interrupts and clears the previous interrupt request.
■
To set up the I
2
C registers:
1. Read the I2CDREC register (x’007E42’) to determine the I
2
C bus controller
status.
2. Since the microcontroller will become a receiver on the next operation, set
the I2CDTRM register (x’007E40’) to x’0000’. This sets STA, STP, ACK,
and the transmission data to 0s. With this setting, the microcontroller returns
an ACK = 0 signal on the ninth clock.