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On-Screen Display
Block Diagram
Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual
154
Panasonic
7.3 Block Diagram
Figure 7-1 OSD Block Diagram
VSYNC
Vertical position
counter
10-bit
VPOL
OSD
HSYNC
HPOL
CANH
Field
detector
EOMON
EOSEL
OSDXI,O
OSCSEL1,0
OSC1,2
4 MHz 48 MHz
PLL
R/W
R/W
SYSCLK
CPU
System clock
IRQ IRQ
addr
addr
data
RAM
DMA block
(
Reads text and
graphics data)
8 Kbytes
Data
decoder
CC,GTC
Font and tile
data read circuit
COL,CCB,HP,VP (attributes)
Dot clock
Clock
sync
circuit
YM
RGB
YS
OSD
registers
FRMON
HCOUNT
Clock
divider
VCLK2,1,0
GEXTE
RAMEND
CROMEND
GROMEND
STC
SHP,SVP
GIHP,GIVP
CIHP,CIVP
EONL
BFLD
Shift register
Text, graphics,
and cursor
ROM
256 Kbytes
Text style
and color
controller
Shutter
controller
Horizontal
position
counter
Color
palettes
UNDF
CAPM
BLINK
MIX display
controller
S,G,COUT
COLB
TRPT
TRPTF
PRYM
GCOL1,0
PALETWE
DAC
YCNT
RGBC
CGPR
YSPOL
Write
Polarity switch
Clock select
Note: indicates the control bit or field.