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SM320F2812-HT
SGUS062A–JUNE 2009–REVISED APRIL 2010
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NOTE
Restriction does not include external hardware wait states
These requirements result in the following XTIMING register configuration restrictions:
Table 6-28. XTIMING Register Configuration Restrictions
(1) (2)
XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING
≥ 1 ≥ 1 ≥ 0 ≥ 1 ≥ 1 ≥ 0 0, 1
(1) Not production tested.
(2) No hardware to detect illegal XTIMING configurations
Examples of valid and invalid timing when using Synchronous XREADY:
Table 6-29. Valid and Invalid Timing when using Synchronous XREADY
(1) (2)
XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING
Invalid 0 0 0 0 0 0 0, 1
Invalid 1 0 0 1 0 0 0, 1
Valid 1 1 0 1 1 0 0, 1
(1) Not production tested.
(2) No hardware to detect illegal XTIMING configurations
• If the XREADY signal is sampled in the Asynchronous mode (USEREADY = 1, READYMODE = 1),
then:
1. Lead: LR ≥ t
c(XTIM)
LW ≥ t
c(XTIM)
2. Active: AR ≥ 2 × t
c(XTIM)
AW ≥ 2 × t
c(XTIM)
NOTE
Restriction does not include external hardware wait states
3. Lead + Active: LR + AR ≥ 4 × t
c(XTIM)
LW + AW ≥ 4 × t
c(XTIM)
NOTE
Restriction does not include external hardware wait states
These requirements result in the following XTIMING register configuration restrictions:
Table 6-30. XTIMING Register Configuration Restrictions
(1) (2)
XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING
≥ 1 ≥ 2 0 ≥ 1 ≥ 2 0 0, 1
(1) Not production tested.
(2) No hardware to detect illegal XTIMING configurations
118 Electrical Specifications Copyright © 2009–2010, Texas Instruments Incorporated
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