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SM320F2812-HT
SGUS062A–JUNE 2009–REVISED APRIL 2010
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The ADC operation is configured, controlled, and monitored by the registers listed in Table 4-4.
Table 4-4. ADC Registers
(1)
NAME ADDRESS SIZE (×16) DESCRIPTION
ADCTRL1 0x00 7100 1 ADC Control Register 1
ADCTRL2 0x00 7101 1 ADC Control Register 2
ADCMAXCONV 0x00 7102 1 ADC Maximum Conversion Channels Register
ADCCHSELSEQ1 0x00 7103 1 ADC Channel Select Sequencing Control Register 1
ADCCHSELSEQ2 0x00 7104 1 ADC Channel Select Sequencing Control Register 2
ADCCHSELSEQ3 0x00 7105 1 ADC Channel Select Sequencing Control Register 3
ADCCHSELSEQ4 0x00 7106 1 ADC Channel Select Sequencing Control Register 4
ADCASEQSR 0x00 7107 1 ADC Auto–Sequence Status Register
ADCRESULT0 0x00 7108 1 ADC Conversion Result Buffer Register 0
ADCRESULT1 0x00 7109 1 ADC Conversion Result Buffer Register 1
ADCRESULT2 0x00 710A 1 ADC Conversion Result Buffer Register 2
ADCRESULT3 0x00 710B 1 ADC Conversion Result Buffer Register 3
ADCRESULT4 0x00 710C 1 ADC Conversion Result Buffer Register 4
ADCRESULT5 0x00 710D 1 ADC Conversion Result Buffer Register 5
ADCRESULT6 0x00 710E 1 ADC Conversion Result Buffer Register 6
ADCRESULT7 0x00 710F 1 ADC Conversion Result Buffer Register 7
ADCRESULT8 0x00 7110 1 ADC Conversion Result Buffer Register 8
ADCRESULT9 0x00 7111 1 ADC Conversion Result Buffer Register 9
ADCRESULT10 0x00 7112 1 ADC Conversion Result Buffer Register 10
ADCRESULT11 0x00 7113 1 ADC Conversion Result Buffer Register 11
ADCRESULT12 0x00 7114 1 ADC Conversion Result Buffer Register 12
ADCRESULT13 0x00 7115 1 ADC Conversion Result Buffer Register 13
ADCRESULT14 0x00 7116 1 ADC Conversion Result Buffer Register 14
ADCRESULT15 0x00 7117 1 ADC Conversion Result Buffer Register 15
ADCTRL3 0x00 7118 1 ADC Control Register 3
ADCST 0x00 7119 1 ADC Status Register
0x00 711C
reserved 4
0x00 711F
(1) The above registers are Peripheral Frame 2 Registers.
64 Peripherals Copyright © 2009–2010, Texas Instruments Incorporated
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