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TNETX4090
ThunderSWITCH II
9-PORT 100-/1000-MBIT/S ETHERNET
SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions (Continued)
10-/100-Mbit/s MAC interface (MII mode) (ports 0–7) (continued)
TERMINAL
I/O
INTERNAL
DESCRIPTION
NAME NO.
I/O
RESISTOR
DESCRIPTION
M00_TXEN
M01_TXEN
M02_TXEN
M03_TXEN
M04_TXEN
M05_TXEN
M06_TXEN
M07_TXEN
D22
B17
B13
B8
H4
L1
V3
AE4
O None
Transmit enable. Indicates valid transmit data on Mxx_TXDn. This signal is synchronous to
Mxx_TCLK.
M00_TXER
M01_TXER
M02_TXER
M03_TXER
M04_TXER
M05_TXER
M06_TXER
M07_TXER
D21
A17
D11
C8
H3
N3
V2
AF4
O None
Transmit error. Allows coding errors to be propagated across the MII. Mxx_TXER is asserted
at the end of an under-running frame, enabling the TNETX4090 to force a coding error.
MII management interface
TERMINAL
I/O
INTERNAL
DESCRIPTION
NAME NO.
I/O
RESISTOR
DESCRIPTION
MDCLK
K26 O Pullup
Serial MII management data clock. Disabled [high-impedance (Z) state] through the use of the
serial input/output (SIO) register. An internal pullup resistor is provided.
MDIO
K25 I/O Pullup
Serial MII management data input/output. Disabled [high-impedance (Z) state] through the use
of the SIO register. An internal pullup resistor is provided.
MRESET
K24 O Pullup
Serial MII management reset. Disabled [high-impedance (Z) state] through the use of the SIO
register. An internal pullup resistor is provided.