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TNETX4090
ThunderSWITCH II
9-PORT 100-/1000-MBIT/S ETHERNET
SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10-/100-Mbit/s MII (ports 0–7)
speed, duplex, and flow-control negotiation
Each individual port can operate at 10 Mbit/s or 100 Mbit/s in half or full duplex, and can indicate (or not) support
of IEEE Std 802.3 flow control. The operating modes for each port can be negotiated between the MACs and
the PHYs after power up, by setting neg in PortxControl. This provides for unmanaged operation, when using
PHYs that support this signaling scheme.
If neg = 1, negotiation is initiated via the Mxx_LINK signal being driven low by the PHY. As long as Mxx_LINK
is low, the MAC indicates the capabilities it wishes the PHY to negotiate with. It outputs on:
Mxx_TXD0 is the desired duplex (0 = half, 1 = full). This signal reflects reqhd in the appropriate PortxControl
register.
Mxx_TXD1 is the desired IEEE Std 802.3 flow-control mode (0 = no pause, 1 = pause required). This signal
reflects the inverse of the value of reqnp in the appropriate PortxControl register.
Mxx_TXD2 is the desired speed (0 = 10 Mbit/s, 1 = 100 Mbit/s required). This signal reflects the inverse of
the value of req10 in the appropriate PortxControl register.
Mxx_TD3 does not take part in the negotiation process and outputs as 0 while Mxx_LINK is low.
As long as Mxx_LINK is low, the PHY outputs on:
Mxx_RXD0 is the result of duplex negotiation (0 = half, 1 = full) that is recorded in the duplex bit of the
appropriate PortxStatus register.
Mxx_RXD1 is the result of flow-control negotiation (0 = no pause, 1 = pause supported) that is recorded
in the pause bit of the appropriate PortxStatus register.
Mxx_RXD2 is the result of speed negotiation (0 = 10 Mbit/s, 1 = 100 Mbit/s supported) that is recorded in
the speed bit of the appropriate PortxStatus register.
Mxx_RXD3 is ignored by the switch when link is low.
If the switch is autobooted via an EEPROM, this negotiation is automatic (if the neg bit of the appropriate
PortxControl register is set to 1 by the EEPROM load). The switch is active and outputs valid requests on
Mxx_TXD0, Mxx_TXD1, and Mxx_TXD2 before Mxx_LINK is taken high by the PHY (see Figure 3).
If, however, a switch requires software initiation, or at a later time, software desires a change in the mode of
a port, it must request the PHY to drive Mxx_LINK low to begin renegotiation. This is achieved by writing to the
control registers within the PHY via the serial MII interface.