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TNETX4090
ThunderSWITCH II
9-PORT 100-/1000-MBIT/S ETHERNET
SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
full-duplex NM port
The NM port can intermix reception and transmission as desired. It is the direction of the NMData access (i.e.,
read or write) that determines whether a byte is removed from the transmit queue or added to the receive queue.
The DIO interface, however, is only half duplex since it cannot do a read and write at the same time.
NM bandwidth and priority
The NM port is capable of transferring a byte to or from NMData once every 80 ns, or 100 Mbit/s. This can be
sustained between the DIO port and the NM ports dedicated receive or receive buffers.
However, the NM port is prioritized lower than the other ports between its receive buffers and the external
memory system so that during periods of high activity, the NM port does not cause frames to be dropped on
the other ports.
interrupt processing
The SRXRDY signal and the nmrx interrupt are set when the receive FIFO is completely empty. This indicates
that the NM port is ready to accept a frame of any length (up to 1535 bytes).
If the host wished to download a sequence of frames, it could use the freebuffs field to determine space
availability.
PHY management interface
This interface gives the user an easy way to implement a software-controlled bit serial MII PHY management
interface.
MII devices that implement the management interface consisting of MDIO and MDCLK can be accessed
through an internal register (see the
TNETX4090 Programmer’s Reference Guide
, literature number SPAU003,
for details on controlling this interface). A third signal, MRESET, is provided to allow hardware reset of PHYs
that support it.
All three terminals have internal pullup resistors since they can be placed in a high-impedance state to allow
another bus master.
The interface does not implement any timing or MII frame formatting. The timing and frame format must be
ensured by the management software setting or clearing the bits within the internal registers in an appropriate
manner. Refer to the IEEE Std 802.3u and the MII device data sheets for the appropriate protocol requirements.