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TMP92CM22
2007-02-16
92CM22-105
3.7.3 SFRs
7 6 5 4 3 2 1 0
Bit symbol TA0RDE I2TA01 TA01PRUN TA1RUN TA0RUN
Read/Write R/W R/W
After reset 0 0 0 0 0
TMRA01
prescaler
UP
counter
(UC1)
UP
counter
(UC0)
Function Double
buffer
0: Disable
1: Enable
IDLE2
0: Stop
1: Operate
0: Stop and clear
1: Run (Count up)
0 Disable 0 Stop and clear
1 Enable 1 Count
Note: The values of bits 4 to 6 of TA01RUN are undefined when read.
7 6 5 4 3 2 1 0
Bit symbol TA2RDE I2TA23 TA23PRUN TA3RUN TA2RUN
Read/Write R/W R/W
After reset 0 0 0 0 0
TMRA23
prescaler
UP
counter
(UC3)
UP
counter
(UC2)
Function Double
buffer
0: Disable
1: Enable
IDLE2
0: Stop
1: Operate
0: Stop and clear
1: Run (Count up)
0 Disable 0 Stop and clear
1 Enable 1 Count
Note: The values of bits 4 to 6 of TA23RUN are undefined when read.
Figure 3.7.4 Register for TMRA
TA0REG double buffer control Count operation
TA01RUN
(1100H)
TMRA01 Run Register
TA2REG double buffer control Count operation
TMRA23 Run Register
TA23RUN
(1108H)