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TMP92CM22
2007-02-16
92CM22-83
CPU Data
Data Size
(Bit)
Start
Address
Data Width in
Memory Side (Bit)
CPU
Address
D15 to D8 D7 to D0
4n + 0 8/16 4n + 0 xxxxx b7 to b0
8 4n + 1 xxxxx b7 to b0 4n + 1
16 4n + 1 b7 to b0 xxxxx
4n + 2 8/16 4n + 2 xxxxx b7 to b0
8 4n + 3 xxxxx b7 to b0
8
4n + 3
16 4n +3 b7 to b0 xxxxx
(1) 4n + 0 xxxxx b7 to b0 8
(2) 4n + 1 xxxxx b15 to b8
4n + 0
16 4n + 0 b15 to b8 b7 to b0
(1) 4n + 1 xxxxx b7 to b0 8
(2) 4n + 2 xxxxx b15 to b8
(1) 4n + 1 b7 to b0 xxxxx
4n + 1
16
(2) 4n + 2 xxxxx b15 to b8
(1) 4n + 2 xxxxx b7 to b0 8
(2) 4n + 1 xxxxx b15 to b8
4n + 2
16 4n + 2 b15 to b8 b7 to b0
(1) 4n + 3 xxxxx b7 to b0 8
(2) 4n + 4 xxxxx b15 to b8
(1) 4n + 3 b7 to b0 xxxxx
16
4n + 3
16
(2) 4n + 4 xxxxx b15 to b8
(1) 4n + 0 xxxxx b7 to b0
(2) 4n + 1 xxxxx b15 to b8
(3) 4n + 2 xxxxx b23 to b16
8
(4) 4n + 3 xxxxx b31 to b24
(1) 4n + 0 b15 to b8 b7 to b0
4n + 0
16
(2) 4n + 2 b31 to b24 b23 to b16
(1) 4n + 0 xxxxx b7 to b0
(2) 4n + 1 xxxxx b15 to b8
(3) 4n + 2 xxxxx b23 to b16
8
(4) 4n + 3 xxxxx b31 to b24
(1) 4n + 1 b7 to b0 xxxxx
(2) 4n + 2 b23 to b16 b15 to b8
4n + 1
16
(3) 4n + 4 xxxxx b31 to b24
(1) 4n + 2 xxxxx b7 to b0
(2) 4n + 3 xxxxx B15 to b8
(3) 4n + 4 xxxxx b23 to b16
8
(4) 4n + 5 xxxxx b31 to b24
(1) 4n + 2 b15 to b8 b7 to b0
4n + 2
16
(2) 4n + 4 b31 to b24 b23 to b16
(1) 4n + 3 xxxxx b7 to b0
(2) 4n + 4 xxxxx b15 to b8
(3) 4n + 5 xxxxx b23 to b16
8
(4) 4n + 6 xxxxx b31 to b24
(1) 4n + 3 b7 to b0 xxxxx
(2) 4n + 4 b23 to b16 b15 to b8
32
4n + 3
16
(3) 4n + 6 xxxxx b31 to b24
xxxxx: During a read, data input to the bus ignored. At write, the bus is at high
impedance and the write strobe signal remains inactive.