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TMP92CM22
2007-02-16
92CM22-144
Figure 3.9.3 Block Diagram of SIO1
Selector
φT0
φT2
φT8
φT32
SC1MOD0
<SC1:0>
Receive buffer 1 (Shift register)
RXDCLK
SC1MOD0
<CTSE>
Prescaler
Selector
TA0TRG
(from TMRA0)
UART
mode
BR1CR
<BR1S3:0>
Baud rate generater
Selector
SC1MOD0
<SM1:0>
Selector
÷ 2
I/O interface mode
SC1CR
<IOC>
Receive control
(UART only ÷ 16)
Transmission
counter
(UART only ÷ 16)
Receive buffer
Transmission
control
INTRX1
INTTX1
Receive buffer 2 (SC1BUF)RB8 Error flag
SC1CR
<OERR> <PERR> <FERR>
Serial channel
interrupt control
TB8
CTS1
(Shared
with PF5)
TXD1
(Shared
with PF3)
Transmission buffe
r
(
SC1BUF
)
RXD1
(Shared
with PF4)
TXDCLK
SC1MOD0
<WU>
f
io
SC1MOD0
<RXE>
SCLK1 output
(Shared
with PF5)
SCLK1 input
(Shared
with PF5)
SIOCLK
Internal data bus
Parity control
SC1CR
<PE> <EVEN>
Serial clock generation circuit
BR1CR<BR1CK1:0>
BR1ADD
<BR1K3:0>
BR1CR
<BR1ADDE>
I/O interface mode
φT0
2 64 4 8 16 32
Prescale
r
φT2
φ
T8 φT32
Interrupt request