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TMP92CM22
2007-02-16
92CM22-95
(2) Page ROM control register (PMEMCR)
The page ROM control register sets page ROM accessing. ROM page accessing is
executed only in block address area 2.
PMEMCR
7 6 5 4 3 2 1 0
Bit symbol OPGE OPWR1 OPWR0 PR1 PR0
Read/Write R/W
After reset 0 0 0 1 0
OPGE Enable bit.
0 = No ROM page mode accessing (Default)
1 = ROM page mode accessing
OPWR [1:0] Specifies the number of waits.
00 = 1 state (n-1-1-1 mode) (n ≥ 2) (Default)
01 = 2 states (n-2-2-2 mode) (n ≥ 3)
10 = 3 states (n-3-3-3 mode) (n ≥ 4)
11 = (Reserved)
Note: Set the number of waits “n” to the control register (BnCSL) in each block address area.
PR [1:0] ROM page size.
00 = 64 bytes
01 = 32 bytes
10 = 16 bytes (Default)
11 = 8 bytes