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TMP92CM22
2007-02-16
92CM22-230
[2] Interrupt controller [3] DMA controller
Address
Name Address Name Address Name Address Name
00D0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
INTE12
INTE3
INTETA01
INTETA23
INTETB0
INTETBO0
INTES0
INTES1
00E0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
INTE45
INTETB1
INTETBO1
INTESB0
INTEP0
00F0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
INTE0AD
INTETC01
INTETC23
INTETC45
INTETC67
SIMC
IIMC
INTWDT
INTCLR
IIMC2
0100H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
DMA0V
DMA1V
DMA2V
DMA3V
DMA4V
DMA5V
DMA6V
DMA7V
DMAB
DMAR
Reserved
[4] Memory controller [5] Clock gear/PLL
Address
Name Address Name Address Name Address Name
0140H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
B0CSL
B0CSH
MAMR0
MSAR0
B1CSL
B1CSH
MAMR1
MSAR1
B2CSL
B2CSH
MAMR2
MSAR2
B3CSL
B3CSH
MAMR3
MSAR3
0150H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
BEXCSL
BEXCSH
0160H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
PMEMCR
10E0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
SYSCR0
SYSCR1
SYSCR2
EMCCR0
EMCCR1
EMCCR2
Reserved
PLLCR
Reserved