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Virtex-5 FPGA ML561 User Guide www.xilinx.com 111
UG199 (v1.2) April 19, 2008
FPGA #3 Pinout
R
QDRII Memory Interface (cont.)
QDR2_Q_BY6_B7 V33 QDR2_Q_BY7_B4 W29
QDR2_Q_BY6_B8 V32 QDR2_Q_BY7_B5 Y31
QDR2_Q_BY7_B0 AB31 QDR2_Q_BY7_B6 W31
QDR2_Q_BY7_B1 Y29 QDR2_Q_BY7_B7 V27
QDR2_Q_BY7_B2 Y28 QDR2_Q_BY7_B8 V28
QDR2_Q_BY7_B3 V29
RLDRAM II Memory Interface
RLD2_A0 AD10 RLD2_CK_BY2_3_N AE11
RLD2_A1 AD9 RLD2_CK_BY2_3_P AF11
RLD2_A10 AC8 RLD2_CS_BY0_1_N AK9
RLD2_A11 AP12 RLD2_CS_BY2_3_N AK8
RLD2_A12 AA9 RLD2_DK_BY0_1_N AH8
RLD2_A13 AA8 RLD2_DK_BY0_1_P AG8
RLD2_A14 AM13 RLD2_DK_BY2_3_N AH10
RLD2_A15 AN13 RLD2_DK_BY2_3_P AH9
RLD2_A16 AA10 RLD2_QK_BY0_N C13
RLD2_A17 AB10 RLD2_QK_BY0_P B13
RLD2_A18 AP14 RLD2_QK_BY1_N K9
RLD2_A19 AN14 RLD2_QK_BY1_P K8
RLD2_A2 AE8 RLD2_QK_BY2_N J7
RLD2_A3 AL10 RLD2_QK_BY2_P H7
RLD2_A4 AL11 RLD2_QK_BY3_N U7
RLD2_A5 AC9 RLD2_QK_BY3_P T8
RLD2_A6 AC10 RLD2_QVLD_BY0_1 F11
RLD2_A7 AM11 RLD2_QVLD_BY2_3 U10
RLD2_A8 AM12 RLD2_REF_N AJ9
RLD2_A9 AB8 RLD2_WE_N AF9
RLD2_BA0 AJ11 RLD2_D_BY0_B0 D11
RLD2_BA1 AK11 RLD2_D_BY0_B1 H8
RLD2_BA2 AD11 RLD2_D_BY0_B2 G8
RLD2_CK_BY0_1_N AG11 RLD2_D_BY0_B3 G10
RLD2_CK_BY0_1_P AG10 RLD2_D_BY0_B4 F10
Table A-3: FPGA #3 Pinout (Continued)
Signal Name Pin Signal Name Pin