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Revision 1.6TTCAN
11.11.02
manual_about.fm
TMC Time Mark Compare
0x0
No Time Mark interrupt is generated.
0x1
Time Mark interrupt if (Time Mark = Cycle Time).
0x2
Time Mark interrupt if (Time Mark = Local Time).
0x3
Time Mark interrupt if (Time Mark = Global Time).
DET Disable External Time Mark Port
one
The Time Mark port is disabled.
zero
The Time Mark port is enabled.
ECS External Clock Synchronisation
The External Clock Synchronisation takes effect when ‘1’ is written to ECS.
ECS will always be read as ‘0’
SWS Stop Watch Source (when edge is detected at the STOP_WATCH_TRIGGER pin)
0x0
Stop Watch is disabled.
0x1
Actual value of Cycle Time is copied to Stop_Watch.
0x2
Actual value of Local Time is copied to Stop_Watch.
0x3
Actual value of Global Time is copied to Stop_Watch.
WGTD Wait for Global Time Discontinuity
one
The node waits for the completion of a Reference Message with
Disc_Bit = ‘1’ after SGT has been set by the CPU. GTDiff is
locked while WGTD is set.
zero
No Global Time Preset is pending.
SGT Set Global Time
The Global Time Preset takes effect when ‘1’ is written to SGT.
SGT will always be read as ‘0’.
The Synchronisation Deviation SD is the difference between NumCfg and NumAct. When the
calculated NumAct deviates by more than 2
(ldSDL +5)
from NumCfg, the drift compensation is
suspended and the GTE interrupt is activated. There is no drift compensation in Level 1.
ECS schedules the updated NumCfg value for activation by the next Reference Message.
SGT schedules the GTDiff value for activation by the next Reference Message.
Setting of ECS and SGT requires EECS to be set and the node to be the actual Time Master.
3.5.21 TT Sync_Mark Register (addresses 0x69 & 0x68)
Sync_MarkSynchronisation Mark
0x0000-0xFFFF
Cycle Time.
The TT Sync_Mark register shows the Sync_Mark captured at the Start of Frame of each
message, measured in Cycle Time. The register is updated when the message becomes valid
and retains its value until the next message becomes valid.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Sync_Mark
rr