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User’s Manual
BOSCH
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Revision 1.6TTCAN
11.11.02
manual_about.fm
When the CPU initiates a data transfer between the IFx Registers and Message RAM, the
Message Handler sets the Busy bit in the respective Command Request Register to ‘1’. After
the transfer has completed, the Busy bit is set back to ‘0’ (see figure 8). If the optional wait-
function is implemented in the module’s CPU interface, the CPU is halted while the Busy bit is
set to ‘1’, see chapter 6.2.
Figure 8: Data Transfer between IFx Registers and Message RAM
4.1.2 Transmission of Messages in Event Driven CAN Communication
If the shift register of the CAN_Core cell is ready for loading and if there is no data transfer
between the IFx Registers and Message RAM, the MsgVal bits in the Message Valid Register
TxRqst bits in the Transmission Request Register are evaluated. The valid Message Object
with the highest priority pending transmission request is loaded into the shift register by the
Message Handler and the transmission is started. The Message Object’s NewDat bit is reset.
After a successful transmission and if no new data was written to the Message Object
(NewDat = ‘0’) since the start of the transmission, the TxRqst bit will be reset. If TxIE is set,
IntPnd will be set after a successful transmission. If the TTCAN has lost the arbitration or if an
error occurred during the transmission, the message will be retransmitted as soon as the CAN
bus is free again. If meanwhile the transmission of a message with higher priority has been
requested, the messages will be transmitted in the order of their priority.
If DAR is set (Disable Automatic Retransmission), TxRqst will be reset when the message is
loaded into the CAN_Core, NewDat will be reset after the successful transmission.
START
WR/RD = 1
Busy = 0
Busy = 1
Read Message Object to IFx
Write IFx to Message RAM
Read Message Object to IFx
No Yes
Write Command Request Register
No
Yes