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Chapter 4 System Support
4.2.3 OPTION ROM MAPPING
4.2.4 PCI INTERRUPTS
ay be generated by on-board PCI devices installed in the PCI slots. For more
information on interrupts incl “System Resources” section
4.4.
4.2.5 PCI POWER MANAGEMENT SUPPORT
T m lies with the PCI Ma tion (rev 1.0). The PCI
Power Man able (PME-) l is d allows complia
a p itiate the an ent ro
4.2.6 P B
T set a bu at a e I bu
4.2.6.1 Hub Link Bus
he chip e MCH and the ICH2. This bus is transparent
software and is not accessible for expansion purposes.
4.2.6.2 LPC Bus
The 82801 ICH2 implements a Low Pin Count (LPC) bus for handling transactions to and from
the 47B367 Super I/O Controller as well as the 82802 Firmware Hub (FWH). The LPC bus
transfers data a nibble (4 bits) at a time at a 33-MHz rate. Generally transparent in operation, the
only consideration required of the LPC bus is during the configuration of DMA channel modes
(see section 4.4.3 “DMA”).
During POST, the PCI bus is scanned for devices that contain their own specific firmware in
ROM. Such option ROM data, if detected, is loaded into system memory’s DOS compatibility
area (refer to the system memory map shown in chapter 3).
E
m
ight interrupt signals (INTA- thru INTH-) are available for use by PCI devices. These signals
or by devices
rrupt mappiuding PCI inte ng refer to the
his syste comp Power nagement Interface Specifica
agement En signa supported by the chipset an nt PCI
nd AGP eripherals to in p mower agem utine.
CI SU -BUSSES
he chip implements two dat s hses t re supplem ntary in operation to the PC s:
T
to
set implements a Hub Link bus between th
Compaq Evo and Workstation Personal Computers
Featuring the Intel Pentium 4 Processor
Second Edition – January 2003
4-8