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Technical Reference Guide
4.3 AGP BUS OVERVIEW
NOTE: For a detailed description of AGP bus operations refer to the AGP Interface
Specification Rev. 2.0 available at the following AGP forum web site:
http://www.agpforum.org/index.htm
The Accelerated Graphics Port (AGP) bus is specifically designed as an economical yet high-
performance interface for graphics adapters, especially those designed for 3D operations. The
AGP interface is designed to give graphics adapters dedicated pipelined access to system memory
for the purpose of off-loading texturing, z-buffering, and alpha blending used in 3D graphics
operations. By off-loading a large portion of 3D data to system memory the AGP graphics adapte
nly requires enough memory for frame buffer (display image
r
) refreshing.
4.3.1
fect. The AGP graphics adapter acts generally as the AGP master, but can also
ehave as a “PCI” target during fast writes from the MCH.
the AGP interface and the PCI interface are as follows:
t
AGP operations is the same linear space used by PCI memory space
commands, but is further specified by the graphics address re-mapping table (GART) of the
north bridge component.
o
BUS TRANSACTIONS
The operation of the AGP bus is based on the 66-MHz PCI specification but includes additional
mechanisms to increase bandwidth. During the configuration phase the AGP bus acts in
accordance with PCI protocol. Once graphics data handling operation is initiated, AGP-defined
protocols take ef
b
Key differences between
♦ Address phase and associated data transfer phase are disconnected transactions. Addressing
and data transferring occur as contiguous actions on the PCI bus. On the AGP bus a reques
for data and the transfer of data may be separated by other operations.
♦ Commands on the AGP bus specify system memory accesses only. Unlike the PCI bus,
commands involving I/O and configuration are not required or allowed. The system memory
address space used in
♦ Data trans ons on GP bu volve e bytes o ultiples of eight bytes. The AGP
m ry addressing protocol uses 8-byte boundaries as opposed to PCI’s 4-byte boundaries.
If a transfer of less than eight bytes is needed, the remaining bytes are filled with arbitrary
d at is discarded by th et.
Pipelined requests are defined by length or size on the AGP bus. The PCI bus defines transfer
s with the FRAME- signal.
h two basic types of transactions on the AGP bus: data requests (addressing) and data
an hese actions are separate from each other.
acti the A s in ight r m
emo
ata th e targ
♦
length
T ere are
tr sfers. T
Compaq Evo and Workstation Personal Computers
Featuring the Intel Pentium 4 Processor
Second Edition - January 2003
4-11