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Technical Reference Guide
The NMI Status Register at I/O port 061h contains NMI source and status data as follows:
MI Status Register 61h
N
Bit Function
7 NMI Status:
0 = No NMI from system board parity error.
1 = NMI requested, read only
6 IOCHK- NMI:
0 = No NMI from IOCHK-
1 = IOCHK- is active (low), NMI requested, read only
5
4
Interval Timer 1, Counter 2 (Speaker) Status
Refresh Indicator (toggles with every refresh)
3 IOCHK- NMI Enable/Disable:
0 = NMI from IOCHK- enabled
1 = NMI from IOCHK- disabled and cleared (R/W)
2 System Board Parity Error (PERR/SERR) NMI Enable:
0 = Parity error NMI enabled
1 = Parity error NMI disabled and cleared (R/W)
1 Speaker Data (R/W)
0 Inteval Timer 1, Counter 2 Gate Signal (R/W)
0 = Counter 2 disabled
1 = Counter 2 enabled
After the active NMI has been processed, status bits <7> or <6> are cleared by pulsing bits <2> or
<3> respectively.
T MI Enable Register (0 able/disable the NMI signal. Writing 80h to
t egister masks generatio NMI-. Note that the lower six bits of register at I/O port 70h
affect RTC operation and sho considered when changing NMI- generation status.
he SMI- (System Management Interrupt) is typically used for power management functions.
r’s SMI handler. The SMI- handler works with the
PM BIOS to service the SMI- according to the cause of the timeout.
Alth s primarily used for power managment the interrupt is also employed for the
uickLock/QuickBlank functions as well.
Functions not related to NMI activity.
he N 70h, <7>) is used to en
his r n of the
uld be
SMI- Generation
T
When power management is enabled, inactivity timers are monitored. When a timer times out,
SMI- is asserted and invokes the microprocesso
A
ough the SMI- i
Q
Compaq Evo and Workstation Personal Computers
Featuring the Intel Pentium 4 Processor
Second Edition - January 2003
4-19