Filter
Top Products
10004281-02 CC1000dm User’s Manual 4-1
. . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C
ARRIER
C
ARD
B
US
I
NTERFACE
4
he CC1000dm carrier card bus interface is provided by using the PLX PCI 6254
(HB6) 66 MHz transparent/non-transparent PCI-to-PCI bridge chip. This device
implements a 64-bit primary data bus and 64-bit secondary data bus interface.
The PCI 6254 also provides read/write data buffering in both directions.
Selecting the appropriate jumper (see page 2-9) allows the CC1000dm carrier card to
operate in systems that do not have a cPCI system controller. In this configuration, the
CC1000dm can reside in any cPCI peripheral slot, though PCI accesses to and from cPCI
are not supported. If a cPCI system controller is present in the system, it will not
acknowledge the CC1000dm on the cPCI bus. In this configuration, all communication
to and from the CC1000dm must be accessed through the PMC slots.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FEATURES
The CC1000dm carrier card bus interface has the following features:
• Supports independent primary and secondary address spaces and address translation
between cPCI and local PCI
• Clock controlled by M66en at 66 MHz
• 64-bit primary data bus and a 64-bit secondary data bus interface
• Hot Swap (ability to remove the CC1000dm carrier card from the system without
powering down, as well as the ability to insert it with the power on)
• Word or byte-organized, 1 kilobit serial ROM
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DATA BUFFERS
Data buffers include the buffers along with the associated data path control logic.
Delayed transaction buffers contain the compare functionality for completing delayed
transactions. The blocks also contain the watchdog timers associated with the buffers.
The data buffers are as follows:
• Four simultaneous posted transactions in each direction
• Four simultaneous delayed transactions in each direction
T