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CARRIER CARD BUS INTERFACE
Arbitration and Device Selection
4-2 CC1000dm User’s Manual 10004281-02
4
• 256-byte downstream posted write buffer
• 256-byte upstream posted write buffer
• 256-byte downstream read data buffer
• 256-byte upstream read data buffer
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ARBITRATION AND DEVICE SELECTION
Arbitration for the secondary PCI bus is provided by the PLX PCI 6254 arbiter. Table 3-5
in the previous chapter shows request/grant assignments for the carrier board second-
ary PCI bus.
The PCI device configuration registers are accessed by connecting the IDSEL signal of
each PCI agent to an A/D signal as defined in the PCI Local Bus Specification Revision
2.3.
Table 3-2 in the previous chapter shows the IDSEL definitions for the CC1000dm.
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CLOCK GENERATION
The PLX PCI 6254 PCI-to-PCI bridge provides clock generation for the secondary local
bus. The s_m66en signal determines whether the frequency of the secondary PCI clock
is 33 MHz or 66 MHz.
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HOT SWAP
The CC1000dm carrier card interface is designed to conform to the Hot Swap require-
ments of the PICMG® 2.1 CompactPCI® Hot Swap Specification/Revision 2.0. This
specification adds features to the standard CC1000dm carrier card interface to allow
orderly insertion and extraction of boards without adversely affecting system opera-
tion. This makes it easy to repair faulty boards or reconfigure a system. Hot Swap also
provides programmatic access to Hot Swap services allowing system reconfiguration
and fault recovery to take place with no system down time and minimum operator
interaction.
Overview
Hot Swap architecture is layered to address a wide range of applications with few
interoperability problems. From a system standpoint, the PICMG® 2.1 CompactPCI® Hot
Swap Specification Revision 2.0 defines minimum capabilities. Additional capabilities