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Selftest Failures
79
tion trap*
1x13 UNEXPECTED_INTERRUPT Data memory break
trap*
1x14 UNEXPECTED_INTERRUPT TLB dirty bit trap*
1x15 UNEXPECTED_INTERRUPT Page Reference trap*
1x16 UNEXPECTED_INTERRUPT Assist emulation
trap*
1x17 UNEXPECTED_INTERRUPT Higher-privilege
transfer trap*
1x18 UNEXPECTED_INTERRUPT Lower-privilege
transfer trap*
1x19 UNEXPECTED_INTERRUPT Taken branch trap*
1x1A UNEXPECTED_INTERRUPT Data memory access
rights trap*
1x1B UNEXPECTED_INTERRUPT Data memory protec-
tion id trap*
1x1C UNEXPECTED_INTERRUPT Unaligned data ref
trap*
Code Name Meaning
1z20 CPU_BASIC CPU basic selftest
1z21 CPU_ALU CPU ALU selftest
1z22 CPU_BR CPU branch selftest
1z23 CPU_ARITH_COND CPU arithmetic con-
dition selftest
1z24 CPU_BIT_OP CPU bit operation
selftest
1z25 CPU_CR CPU control regis-
ters selftest
1z26 CPU_EXT_INT CPU external inter-
rupt selftest
1z27 CPU_ITIME CPU itimer selftest
1z28 CPU_MULTI_MEDIA CPU multi-media
selftest
1z29 CPU_SHADOW CPU Shadow register
selftest
1z2A CPU_DIAGS CPU Diagnose regis-
ter selftest
1z2B CPU_RDRS CPU Remote Diagnose
register selftest
1z2C CPU_BYPASS CPU bypass selftest
1z30 STARTING_EST Starting Early Self-
test
1z31 EST_SKIPPED Early Selftest
skipped
1z32 BAD_CPU_TEST_MODE
1z3C CPU_INIT Initialize the CPU
1z3E EXITING_EST Exiting Early Selft-
est
1z3F CACHE_LOAD_ERROR
1z40-1z7F CPU_RDR_WARN where 40 = rdr0 ...
7F = rdr 31
1zA0 COPROC CPU COPROC selftest
1zA1 COPROC_REG COPROC register
selftest
1zA2 COPROC_INSTR COPROC instruction
selftest
1zA3 COPROC_TRAPS COPROC trap selftest
1zA4 COPROC_MISC COPROC miscella-
neous selftest
1xA5 COPROC_BYPASS COPROC bypass selft-
est
1zAF FPU_S_DISABLED FPUs are disabled
1zB0 TLB_INIT Initialize the TLB
1zB0 TLB_INIT_ERR TLB initialization
failure
1zB1 TLB_RAM TLB RAM selftest
1xB2 TLB_TRANS TLB translation
selftest