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Writing to the Registers
You can write to the following RF multiplexer registers:
• Status/Control register (base + 04
h
)
• Bank 0 Channel Enable register (base + 08
h
)
• Bank 1 Channel Enable register (base + A
h
)
Status/Control
Register
The only write allowed to the Status/Control register (base + 04
h
) is to bit 0.
Writing a “1” to bit 0 resets the multiplexer to its power-on state with all
channels open and terminated and both commons open.
Channel Enable
Registers
Writes to the Channel Enable registers (base + 08
h
and base + A
h
) enabling
you to open or close the desired channel (see Register Defintions at the
beginning of this chapter). For example, write a “1” to bit 2 of the bank 0
Channel Enable register to close channel 02. Or, write a “1” to bit 3 of the
Bank 1 Channel Enable register to close channel 13. Writing a “0” to bits
0 - 3 results in all channels open and terminated and the common open.
Only one channel per bank can be closed at a time. Any bit pattern not
shown in Register Defintions at the beginning of this chapter, results in the
lowest-numbered channel being closed.
Appendix B HP E1366A/E1367A Multiplexer Registers 67