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Electrical Specifications
150 Intel® Xeon® Processor E5-1600 v2/E5-2600 v2 Product Families
Datasheet Volume One of Two
8. For Vin between 0 and Vih.
Note:
1. These signals are measured between VIL and VIH.
2. The signal edge rate must be met or the signal must transition monotonically to the asserted state.
Table 7-18. SMBus DC Specifications
Symbol Parameter Min Max Units Notes
V
IL
Input Low Voltage 0.3*V
TT
V
V
IH
Input High Voltage 0.7*VTT V
V
Hysteresis
Hysteresis 0.1*VTT V
V
OL
Output Low Voltage 0.2*V
TT
V
R
ON
Buffer On Resistance 4 14 Ω
I
L
Leakage Current 50 200 μA
Output Edge Rate (50 ohm to V
TT
, between V
IL
and V
IH
)
0.05 0.6 V/ns
Table 7-19. JTAG and TAP Signals DC Specifications
Symbol Parameter Min Max Units Notes
V
IL
Input Low Voltage 0.3*V
TT
V
V
IH
Input High Voltage 0.7*V
TT
V
V
IL
Input Low Voltage: PREQ_N 0.4*V
TT
V
V
IH
Input High Voltage: PREQ_N 0.8*V
TT
V
V
OL
Output Low Voltage 0.2*V
TT
V
V
Hysteresis
Hysteresis 0.1*V
TT
V
R
ON
Buffer On Resistance
BPM_N[7:0], PRDY_N, TDO
414Ω
I
IL
Input Leakage Current 50 200 μA
Input Edge Rate
Signals: BPM_N[7:0], EAR_N, PREQ_N, TCK,
TDI, TMS, TRST_N
0.05 V/ns 1, 2
Output Edge Rate (50 ohm to V
TT
)
Signal: BPM_N[7:0], PRDY_N, TDO
0.2 1.5 V/ns 1
Table 7-20. Serial VID Interface (SVID) DC Specifications (Sheet 1 of 2)
Symbol Parameter Min Typ Max Units Notes
V
TT
CPU I/O Voltage VTT - 3% 1.0 VTT + 3% V
V
IL
Input Low Voltage
Signals SVIDDATA, SVIDALERT_N
0.4*V
TT
V1
V
IH
Input High Voltage
Signals SVIDDATA, SVIDALERT_N
0.7*V
TT
V1
V
OL
Output Low Voltage
Signals SVIDCLK, SVIDDATA
0.3*V
TT
V1
V
Hysteresis
Hysteresis 0.05*V
TT
V1
R
ON
Buffer On Resistance
Signals SVIDCLK, SVIDDATA
414Ω 2