Filter
Top Products
Interfaces
56 Intel® Xeon® Processor E5-1600 v2/E5-2600 v2 Product Families
Datasheet Volume One of Two
The same conversion formula used for DRAM Power Limiting (see Section 2.5.2.6.9)
should be applied for encoding or programming the ‘Control Time Window’ in bits
[23:17].
2.5.2.6.26 Package Power Limits for Multiple Turbo Modes
This feature allows the PECI host to program two power limit values to support multiple
turbo modes. The operating systems and drivers can balance the power budget using
these two limits. Two separate PECI requests are available to program the lower and
upper 32 bits of the power limit data shown in Figure 2-36. The units for the Power
Limit and Control Time Window are determined as per the Package Power SKU Unit
settings described in Section 2.5.2.6.13 while the valid range for power limit values are
determined by the Package Power SKU settings described in w are determined as per
the Package Power SKU Unit settings described in Section 2.5.2.6.14. Setting the
Clamp Mode bits is required to allow the cores to go into power states below what the
operating system originally requested. The Power Limit Enable bits should be set to
enable the power limiting function. Power limit values, enable and clamp mode bits can
all be set in the same command cycle. All RAPL parameter values including the power
limit value, control time window, clamp mode and enable bit will have to be specified
correctly even if the intent is to change just one parameter value when programming
over PECI.
Intel recommends exclusive use of just one entity or interface, PECI for instance, to
manage all processor package power limiting and budgeting needs. If PECI is being
used to manage package power limiting activities, BIOS should lock out all subsequent
inband package power limiting accesses by setting bit 31 of the
PACKAGE_POWER_LIMIT MSR and CSR to ‘1’. The ‘power limit 1’ is intended to limit
processor power consumption to any reasonable value below TDP and defaults to TDP.
‘Power Limit 1’ values may be impacted by the processor heat sinks and system air
flow. Processor ‘power limit 2’ can be used as appropriate to limit the current drawn by
the processor to prevent any external power supply unit issues. The ‘Power Limit 2’
should always be programmed to a value (typically 20%) higher than ‘Power Limit 1’
and has no default value associated with it.
Though this feature is disabled by default and external programming is required to
enable, initialize and control package power limit values and time windows, the
processor package will still turbo to TDP if ‘Power Limit 1’ is not enabled or initialized.
‘Control Time Window#1’ (Power_Limit_1_Time also known as Tau) values may be
programmed to be within a range of 250 mS-40 seconds. ‘Control Time Window#2’
(Power_Limit_2_Time) values should be in the range 3 mS-10 mS.
The same conversion formula used for the DRAM Power Limiting feature (see
Section 2.5.2.6.9) should be applied when programming the ‘Control Time Window’ bits
[23:17] for ‘power limit 1’ in Figure 2-36. The ‘Control Time Window’ for ‘power limit 2’
can be directly programmed into bits [55:49] in units of mS without the aid of any
conversion formulas.
Figure 2-35. Power Limit Data for VCC Power Plane
VCC Power Plane Power Limit Data
Power Limit
Enable
1523
VCC Plane Power Limit
14 0
Clamp
Mode
16
Control Time
Window
1731
RESERVED
24