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Datasheet 31
Electrical Specifications
The power pod provides a selectable output voltage controlled via multiple binary weighted
Voltage Identification (VID) inputs. The VID value (high = 1; low = 0) is defined in Table 2-23.
VID pads shall be considered as LVTTL inputs to the power pod, having resistive pull-ups (5 kΩ)
included inside the power pod to the internal 3.3 V power supply. The VID pads on the power
connector tab will be pulled low with 10 Ω resistors that are internal to the processor. The 10 Ω
resistive pulldowns are controlled by Intel and will not be externally adjustable.
The processor has several power levels as shown in Table 2-24 and in Figure 2-5. Full power to the
processor is defined in Table 2-2.
Table 2-23. Processor Core Voltage Identification Code
1
NOTES:
1. Nominal settings require regulation to ±7% at V
CC,PS
pins at the power tab under all conditions.
Processor Pins: 0 = Connected to GND; 1 = Open
V
CC
(VDC)
VID4 VID3 VID2 VID1 VID0
1 1 1 1 1 Output Off
11 1 1 00.95
1 1 1 0 1 0.975
11 1 0 01.0
1 1 0 1 1 1.025
11 0 1 01.05
1 1 0 0 1 1.075
11 0 0 01.1
1 0 1 1 1 1.125
10 1 1 01.15
1 0 1 0 1 1.175
10 1 0 01.2
1 0 0 1 1 1.225
1 0 0 1 0 1.250
1 0 0 0 1 1.275
10 0 0 01.3
0 1 1 1 1 1.325
01 1 1 01.35
0 1 1 0 1 1.375
01 1 0 01.4
0 1 0 1 1 1.425
01 0 1 01.45
0 1 0 0 1 1.475
01 0 0 01.5
0 0 1 1 1 1.525
00 1 1 01.55
0 0 1 0 1 1.575
00 1 0 01.6
0 0 0 1 1 1.625
00 0 1 01.65
0 0 0 0 1 1.675
00 0 0 01.7