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4 Datasheet
6.1.3 SMBus Device Addressing..................................................................... 81
6.2 Processor Information ROM................................................................................82
6.3 Scratch EEPROM ...............................................................................................85
6.4 Processor Information ROM and Scratch EEPROM Supported
SMBus Transactions ...........................................................................................85
6.5 Thermal Sensing Device .....................................................................................86
6.6 Thermal Sensing Device Supported SMBus Transactions ................................. 87
6.7 Thermal Sensing Device Registers..................................................................... 88
6.7.1 Thermal Reference Registers ................................................................88
6.7.2 Thermal Limit Registers .........................................................................89
6.7.3 Status Register.......................................................................................89
6.7.4 Configuration Register ...........................................................................89
6.7.5 Conversion Rate Register ......................................................................90
A Signals Reference............................................................................................................ 91
A.1 Alphabetical Signals Reference .......................................................................... 91
A.1.1 A[49:3]# (I/O).......................................................................................... 91
A.1.2 A20M# (I) ...............................................................................................91
A.1.3 ADS# (I/O).............................................................................................. 91
A.1.4 AP[1:0]# (I/O) ......................................................................................... 91
A.1.5 ASZ[1:0]# (I/O) .......................................................................................91
A.1.6 ATTR[3:0]# (I/O).....................................................................................92
A.1.7 BCLKp/BCLKn (I) ...................................................................................92
A.1.8 BE[7:0]# (I/O) ......................................................................................... 92
A.1.9 BERR# (I/O) ...........................................................................................93
A.1.10 BINIT# (I/O)............................................................................................ 94
A.1.11 BNR# (I/O) .............................................................................................94
A.1.12 BPM[5:0]# (I/O) ...................................................................................... 94
A.1.13 BPRI# (I) ................................................................................................94
A.1.14 BR[0]# (I/O) and BR[3:1]# (I)..................................................................94
A.1.15 BREQ[3:0]# (I/O).................................................................................... 95
A.1.16 CCL# (I/O).............................................................................................. 96
A.1.17 CPUPRES# (O)...................................................................................... 96
A.1.18 D[127:0]# (I/O) ....................................................................................... 96
A.1.19 D/C# (I/O)...............................................................................................96
A.1.20 DBSY# (I/O) ........................................................................................... 96
A.1.21 DBSY_C1# (O)....................................................................................... 96
A.1.22 DBSY_C2# (O)....................................................................................... 97
A.1.23 DEFER# (I).............................................................................................97
A.1.24 DEN# (I/O) .............................................................................................97
A.1.25 DEP[15:0]# (I/O).....................................................................................97
A.1.26 DHIT# (I) ................................................................................................97
A.1.27 DPS# (I/O)..............................................................................................98
A.1.28 DRDY# (I/O)........................................................................................... 98
A.1.29 DRDY_C1# (O) ......................................................................................98
A.1.30 DRDY_C2# (O) ......................................................................................98
A.1.31 DSZ[1:0]# (I/O).......................................................................................98
A.1.32 EXF[4:0]# (I/O) .......................................................................................98
A.1.33 FCL# (I/O) ..............................................................................................99
A.1.34 FERR# (O) ............................................................................................. 99
A.1.35 GSEQ# (I) ..............................................................................................99
A.1.36 HIT# (I/O) and HITM# (I/O) ....................................................................99