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Intel NetStructure
®
MPCBL0010 Single Board Computer
October 2006 Technical Product Specification
Order Number: 304120 163
Telecom Clock—MPCBL0010 SBC
• 2.048 MHz
• 2.048 MHz
• 4.096 MHz
• 6.312 MHz
• 8.192 MHz,
• 8.592 MHz
• 11.184 MHz
• 19.44 MHz
• 34.368 MHz
• 44.735 MHz.
Note: Only one frequency per AdvancedMC module can be selected.
12.3.3 Recovered Clock Selection
Each AdvancedMC module has one clock output. This clock can be forwarded to CLK3A
and/or CLK3B on the AdvancedTCA backplane without changing the frequency. The
output level converters convert from LVTTL to M-LVDS. The M-LVDS buffers can be tri-
stated by the telecom clock module using its I
2
C interface.
12.3.4 Configuration
The clock outputs are disabled by default. The following basic and operational
configurations are necessary:
12.3.4.1 Operational Configuration
For the operational configuration, the following parameters must be defined:
• Frequency of the redundant reference clock (CLK1=8 kHz or CLK2=19.44 MHz)
• Which AdvancedMC modules are installed and which frequency of the reference
clock for the transmission is required
• Which AdvancedMC clock is used as a source of the system reference clock, and to
which clock bus it has to be connected
• Operating mode of the PLL (normal, holdover, or free-run)
• Switchover by PLL unlock enabled
• Switchover by PLL holdover enabled
12.3.5 Alarm Handling
The following alarms are available:
• Primary redundant clock lost (PRI_LOS)
• Secondary redundant clock lost (SEC_LOS)
• PLL is in the holdover mode (HOLDOVER)
• PLL is in unlock (UNLOCK)
A change of status to any of the alarms will cause an interrupt. The interrupt is
deactivated when the status register is read.