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Processor and Chipset Intel® SHG2 DP Server Board Technical Product Specification
Intel Order Number C11343-001 Revision 1.0
6
2. Processor and Chipset
2.1 Overview
The Intel SHG2 Server Board consists of one to two identical Intel Xeon processors, the Grand
Champion LE chipset, and support circuitry. The baseboard houses two surface mount zero
insertion force (ZIF) processor sockets and one embedded processor voltage regulator module
(VRMs) to power one or both processors. The ServerWorks* Grand Champion LE chipset
provides the 36-bit address/64-bit data processor host bus interface, operating at 100 MHz in
the AGTL+ signaling environment. The Grand Champion Memory and I/O Controller (CMIC-LE)
provides an integrated memory controller, a high-speed I/O connection (IMB) to the PCI-X
bridge (CIOB-X2) and a connection (Thin IMB) to the south bridge (CSB5) for legacy devices
and the PCI segment. The server board supports up to 12 GB of ECC memory, using 2GB
DDR-registered PC1600 or PC2100 SDRAM DIMMs.
Additional descriptions and features include the following:
•
ServerWorks Grand Champion LE chipset providing an integrated I/O bridge and
memory controller, and a flexible I/O subsystem core (PCI) optimized for multiprocessor
systems and standard high-volume (SHV) servers.
•
Dual (603 pin) processor sockets that accept the Intel Xeon processors.
•
Processor host bus AGTL+ supported circuitry, including termination power supply.
•
Integrated APIC signals support.
•
Miscellaneous logic for reset configuration, processor presence detection, ITP port, and
server management.
2.2 Processor Support
SHG2 specifically supports Intel
Xeon processors from 1.8 GHz to 2.6 GHz, with 512 KB of L2
advanced transfer cache.
The processor is packaged in a 603-pin micro- Pin-Grid Array (PGA) and provides an integrated
heat spreader (IHS) for heat sink attachment.
The Intel Xeon processor socket that conforms to the 603-pin Socket Design Guidelines is a
surface mount technology (SMT); ZIF socket using soldered ball attachment (BGA) to the
platform.
As with previous versions of Intel
®
Pentium
®
Pro processors, the Intel Xeon processor external
interface is designed to be DP-ready. Each processor contains a local advanced
programmable interrupt controller (APIC) section for interrupt handling. When two processors
are installed, both processors must be of identical revision, core voltage, cache voltage, and
bus/core speeds.
Note: When using only one processor in the system, install the processor into the primary
socket (PROC1, closest to the corner of the board). This will enable on-die termination on the
end-agent processor the for system to function properly. The BMC will not allow DC power to