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Intel® SHG2 DP Server Board Technical Product Specification Error Reporting and Handling
Revision 1.0 Intel Order Number C11343-001
41
code of 1-3-1-1 is generated. The dash between the numbers defines an audible pause that
delimits the sequence.
POST codes will occur prior to the video display being initialized. To assist in determining the
fault, a unique beep-code is derived from these checkpoints as follows:
1. The 8-bit test point is broken down to four 2-bit groups.
2. Each group is made one-based (1 through 4).
3. One to four beeps are generated based on each group’s 2-bit pattern.
Example:
Checkpoint 04Bh is broken down to: 01 00 10 11
And the beep code is: 2 – 1 – 3 –4
Table 30. Standard BIOS POST Codes
CP Beeps Reason
02 Verify Real Mode
04 Get Processor type
06 Initialize system hardware
08 Initialize chipset registers with initial POST values
09 Set in POST flag
0A Initialize Processor registers
0B Enable Processor cache
0C Initialize caches to initial POST values
0E Initialize I/O
0F Initialize the local bus IDE
10 Initialize Power Management
11 Load alternate registers with initial POST values
12 Restore Processor control word during warm boot
14 Initialize keyboard controller
16 1-2-2-3 BIOS ROM checksum
18 8254 timer initialization
1A 8237 DMA controller initialization
1C Reset Programmable Interrupt Controller
20 1-3-1-1 Test DRAM refresh
22 1-3-1-3 Test 8742 Keyboard Controller
24 Set ES segment register to 4GB
28 1-3-3-1 Auto-size DRAM, system BIOS stops execution if it does not detect any usable memory
2A Clear 8 MB base RAM
2C 1-3-4-1 Base RAM failure, BIOS stops execution here if entire memory is bad
32 Test Processor bus-clock frequency