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General Specifications Intel® SHG2 DP Server Board Technical Product Specification
Intel Order Number C11343-001 Revision 1.0
76
Item Description Min Max Units
T
pwok_off
Delay from PWOK deasserted to output
voltages (3.3V, 5V, 12V, -12V) dropping out
of regulation limits.
1
msec
T
pwok_low
Duration of PWOK being in the deasserted
state during an off/on cycle using AC or the
PSON signal.
100
msec
T
sb_vout
Delay from 5VSB being in regulation to O/Ps
being in regulation at AC turn on.
50 1000
msec
Figure 16. Turn On/Off Timing
9.3.2.2 Voltage Recovery Timing Specifications
The power supply must conform to the following specifications for voltage recovery timing under
load changes:
1. Voltage shall remain within +/- 5% of the nominal set voltage on the +5 V, +12 V, 3.3 V, -5 V
and –12 V outputs, during instantaneous changes in load shown in the table below.
Vout
PWOK
5VSB
PSON
T
sb_on_del
ay
T
AC_on_dela
y
T
pwok_on
T
vout_holdu
p
T
pwok_holdup
T
pson_on_dela
y
T
sb_on_delay
T
pwok_on
T
pwok_off
T
pwok_off
T
pson_pwok
T
pwok_low
T
sb_vout
A
C turn on/off cycle
PSON turn on/off cycle