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HighWire HW400c/2 User Reference Guide Rev 1.0
3.2.3 Host PCI B
or and CompactPCI host, as well as between the PTMC
ites and the CompactPCI host. The MV64462 device acts as a PCI-to-PCI bridge
he HW400c/2 supports a 64-bit-wide bus operating at 33 or 66 MHz. PCI-X
d; however 100/133 MHz operation is not supported.
3.2.3.1 Operation
s
nt on the backplane,
is pin is defined as GND. If the PCI bus is not present on the backplane, then it
, and
f the PCI bus (see
ection 4.2.10). The software must read this register to determine whether the PCI
J1.
his jumper is labeled IGNP (part of J7, see Section 3.1.5), and when installed, the
CI reset and clock signals for MV64462 PCI bus 0 are generated internally.
If a Slot 1 card is present and the IGNP jumper is installed, the HW400c/2 will not be
able to communicate with the Slot 1 card.
3.2.4 Local PCI
terface between the processor and the two PTMC sites. The local PCI bus is 32-
nd
us
The Marvell Discovery III (MV64462) host PCI bus (PCI bus 0) provides an
interface between the process
s
between the two PCI buses.
T
operation at 66 MHz is supporte
Without CompactPCI Bus
The HW400c/2 supports the PICMG 2.16 R1.0 specification’s requirement that a
PICMG 2.16 compliant node card must have the ability to operate without the
presence of the CPCI bus. CPCI connectors J1 and J2 are present as they provide
power and geographic addressing information; however pin B6 of J1 is redefined a
signal PCI_PRSNT# in PICMG 2.16. When the PCI bus is prese
th
must leave this pin floating (there is a 10K pull-up on the node).
The state of the PCI_PRSNT# signal is sensed at power-up (or hot-swap) and, if
inactive, the backplane PCI signals are ignored, enabling the board to boot up
normally. The primary PCI signals from the MV64462 are tri-stated in this case
the precharge voltage is switched from 1.0V to VIO (3.3V or 5V) to prevent floating
signals. The PCI Status Register (PSR) provides the status o
S
bus is present or not and configure the board appropriately.
The HW400c/2 can also boot up without the slot 1 card in a CompactPCI chassis. A
jumper enables this feature, regardless of the state of the PCI_PRSNT# pin on
T
P
Bus
The Marvell Discovery III (MV64462) local PCI bus (PCI bus 1) provides an
in
bits wide and operates in PCI mode at 33-66 MHz, or PCI-X mode at 66-133 MHz.
The PCI-X 133 MHz speed is allowed when only one PTMC module is installed,
a
!
stalled at Site B. If two PCI-X capable modules are installed, or a PCI-X
apable module is installed at Site A, the bus frequency is automatically forced to
100 MHz.
it must be in
c
October 10, 2006 Copyright 2006, SBE, Inc. Page 18