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HighWire HW400c/2 User Reference Guide Rev 1.0
3.6.7 IPMI System Power Supply ......................................................................................42
3.6.8 IPMI Firmware EEPROMs .......................................................................................42
3.6.9 Zircon PM Reset........................................................................................................43
3.6.10 IMPI Get Device ID ................................................................................................43
3.7 Hot Swap Support...............................................................................................................44
3.7.1 Hot Swap on J1 and J2 ..............................................................................................44
3.7.2 Hot Swap on J3..........................................................................................................44
3.7.3 Hot Swap on J4..........................................................................................................44
3.7.4 Hot Swap on J5..........................................................................................................44
3.7.5 Hot Swap Sequence...................................................................................................45
4 Programming Information.........................................................................................................46
4.1 HW400c/2 Memory Map....................................................................................................46
4.2 CPLD Registers ..................................................................................................................47
4.2.1 Clock Select Register (CSR) .....................................................................................48
4.2.2 Board Status Register (BSR).....................................................................................49
4.2.3 LED Register A (LEDA)...........................................................................................49
4.2.4 Memory Option Register (MOR) ..............................................................................50
4.2.5 Geographic Addressing Register (GAR)...................................................................50
4.2.6 PTMC Reset Register (PRR).....................................................................................51
4.2.7 PTMC Control Register (PCR)..................................................................................51
4.2.8 Board Option Register (BOR)...................................................................................52
4.2.9 General Purpose Register (GPR)...............................................................................52
4.2.10 PCI Status Register (PSR).......................................................................................53
4.2.11 Extended Type Register (ETR) ...............................................................................53
4.2.12 Hardware Revision Register (HRR)........................................................................54
4.2.13 PLL Configuration Register A (PLLA)...................................................................54
4.2.14 PLL Configuration Register B (PLLB) ...................................................................55
4.2.15 LED Register B (LEDB) .........................................................................................56
4.2.16 Device Control Register (DCR) ..............................................................................57
4.2.17 CPU Timer Register (CTR).....................................................................................57
4.2.18 Warm Reset Register (WRR) ..................................................................................58
4.2.19 SPI Page Register (SPR) .........................................................................................58
4.2.20 SPI Address Register (SAR)....................................................................................58
4.2.21 SPI Read Byte Offset Register (SOR).....................................................................59
4.2.22 Read Byte Count Register (RBC)............................................................................59
4.2.23 Write Byte Count Register (WBC)..........................................................................60
4.2.24 SPI Data Registers (SDR0 – SDR7)........................................................................60
4.2.25 SPI Error and Status Register (SESR).....................................................................61
4.2.26 EEPROM Address Register (EAR).........................................................................61
4.2.27 EEPROM Operation/Status Register (EOSR).........................................................62
4.2.28 EEPROM Data Registers (EDR0 – EDR1).............................................................63
4.3 Accessing the Serial EEPROM...........................................................................................63
4.3.1 Reading an EEPROM Address..................................................................................63
4.3.2 Writing an EEPROM Address...................................................................................64
4.4 Accessing the SPI Interface ................................................................................................64
4.4.1 Registers in the CPLD...............................................................................................64
4.4.2 BCM5388 Registers Access Rules............................................................................64
October 10, 2006 Copyright 2006, SBE, Inc. Page vii