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HighWire HW400c/2 User Reference Guide Rev 1.0
4.2 CPLD Registers
ogrammable Logic Device) registers are 8-bit registers that
are accessible by the system controller.
Nam De
Offset
ess
)
c
All CPLD (Complex Pr
1: All reserved locations and bits are set to zero after a reset to the CPLD.
: Check individual register descriptions for default register values after reset. 2
Table 29. CPLD Registers
e scription
Addr
(Hex
Fun tion
RES0 Reser egac 00 Re ) 3 Reserved -3 ved (L y HW4 gisters 00-0
CSR Clock Select Register 04 Read/Write
BSR Board Status Register 05 Read/Write
LEDA LED Register A 06 Read/Write
MOR Memory Option Register 07 Read Only
G ly AR Geographic Addressing Register 08 Read On
P 09 Read/Write RR PTMC Reset Register
PCR PTMC Control Register 0A Read/Write
RESB-C Reserved (Legacy HW400 Registers) 0B-0C Reserved
BOR Board Option Register 0D Read Only
G E Read/Write PR General Purpose Register 0
PSR PCI Status Register 0F Read Only
ETR Extended Type Register 10 Read Only
HRR Hardware Revision Register 11 Read Only
P C uLLA PLL onfig ration Register A 12 Read Only
PLLB C uPLL onfig ration Register B 13 Read Only
LEDB LED Register B 14 Read/Write
D ice tCR Dev Con rol Register 15 Read/Write
CTR CPU T Rimer egister 16 Read Only
WRR Warm set ster 17 Read/Write re Regi
RES rv r18-19 Rese ed fo future use 18-19 Reserved
SPR SPI Page Re 1A Read/Write gister
SAR SPI Ad sdres Register 1B Read/Write
SOR SPI Read Byte Offset Register 1C Read/Write
RBC Read Byte Count Register 1D Read/Write
W BBC Write yte Count Register 1E Read/Write
SESR SPI Err nor a d Status Register 1F Read Only
SDR SPI Da eta R gisters 20-27 Read/Write
E R EEPROM Ad gister 28 Read/Write A dress Re
EOSR EEPROM Operation/Status Register 29 Read/Write
E aDR EEPROM D ta Registers 2A-2B Read/Write
RES2C-
F
Reserv d for e 2C-FF Reserved
F
e future us
October 10, 2006 Copyright 2006, SBE, Inc. Page 47