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HighWire HW400c/2 User Reference Guide Rev 1.0
3.2.7.4 CT Bus Controller
The Agere T8110L CT bus controller on the HW400c/2 board is accessed and
programmed via the device bus. It also has a data bus width of 16 bits. Burst
reads/writes are not supported by the T8110L. See Section 3.3 for details about the
CT Bus Controller functions.
3.2.7.5 CPLD
The Complex Programmable Logic Device (CPLD) registers are also accessed via
the device bus, using an 8-bit data bus width. Miscellaneous signals such as resets
and mezzanine card selection logic are monitored and controlled by the CPLD
registers. The CPLD supports burst reads and writes. See Section 4.2 for details
about CPLD register functions.
3.2.8 Watchdog Timer
The Marvell MV64462 Discovery III system controller contains an internal 32-bit
Watchdog Timer that can be configured as a source of interrupt to either the
MPC744X processor or to the CompactPCI host through the PCI interrupt output.
The IPMI controller can also detect a Watchdog timeout by checking the appropriate
GPIO bit (see Table 22 in Section 3.6).
3.2.9 Reset
The following types of reset are available:
• Power–on reset. Resets the entire board during hot-swap or power-up.
• Optional external pushbutton reset. See Section 3.2.9 for details.
• Host PCI reset. This reset is routed through the Early Power CPLD, allowing
the host on the CompactPCI bus to reset all devices on the HW400c/2 board.
• Individual device reset. The PTMC sites, the T8110L, the Ethernet Switch
and PHYs and the Disk on Chip can all be individually reset via the CPLD
register bits (see Section 4.2.16)
• Software reset (warm reset). Initiated by writing to the CPLD’s Warm Reset
Register (WRR, see Section 4.2.18), resets the CPU, System Controller, and
all on board devices. Host PCI reset signal is not affected by warm reset.
October 10, 2006 Copyright 2006, SBE, Inc. Page 23