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Table 127. CPLD Macrocell Asynchronous Clock Mode Timing (5V Devices)
Table 128. CPLD Macrocell Asynchronous Clock Mode Timing (3V Devices)
Symbol Parameter Conditions Min Max
PT
Aloc
Turbo
Off
Slew
Rate
Unit
f
MAXA
Maximum Frequency
External Feedback
1/(t
SA
+t
COA
)
38.4 MHz
Maximum Frequency
Internal Feedback (f
CNTA
)
1/(t
SA
+t
COA
–10)
62.5 MHz
Maximum Frequency
Pipelined Data
1/(t
CHA
+t
CLA
)
71.4 MHz
t
SA
Input Setup Time 7 + 2 + 10 ns
t
HA
Input Hold Time 8 ns
t
CHA
Clock Input High Time 9 + 10 ns
t
CLA
Clock Input Low Time 9 + 10 ns
t
COA
Clock to Output Delay 21 + 10 – 2 ns
t
ARDA
CPLD Array Delay Any macrocell 11 + 2 ns
t
MINA
Minimum Clock Period
1/f
CNTA
16 ns
Symbol Parameter Conditions Min Max
PT
Aloc
Turbo
Off
Slew
Rate
Unit
f
MAXA
Maximum Frequency
External Feedback
1/(t
SA
+t
COA
)
21.7 MHz
Maximum Frequency
Internal Feedback (f
CNTA
)
1/(t
SA
+t
COA
–10)
27.8 MHz
Maximum Frequency
Pipelined Data
1/(t
CHA
+t
CLA
)
33.3 MHz
t
SA
Input Setup Time 10 + 4 + 20 ns
t
HA
Input Hold Time 12 ns
t
CHA
Clock High Time 17 + 20 ns
t
CLA
Clock Low Time 13 + 20 ns
t
COA
Clock to Output Delay 36 + 20 – 6 ns
t
ARD
CPLD Array Delay Any macrocell 25 + 4 ns
t
MINA
Minimum Clock Period
1/f
CNTA
36 ns