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2PeripheralArchitecture
2.1ClockControl
2.2MemoryMap
2.3SignalDescriptions
PeripheralArchitecture
TheDDR2memorycontrollercangluelesslyinterfacetomoststandardDDR2SDRAMdevicesand
supportssuchfeaturesasself-refreshmodeandprioritizedrefresh.Inaddition,itprovidesflexibility
throughprogrammableparameterssuchastherefreshrate,CASlatency,andmanySDRAMtiming
parameters.
ThefollowingsectionsdescribethearchitectureoftheDDR2memorycontrolleraswellashowto
interfaceandconfigureittoperformreadandwriteoperationstoDDR2SDRAMdevices.Also,Section3
providesadetailedexampleofinterfacingtheDDR2memorycontrollertoacommonDDR2SDRAM
device.
TheDDR2memorycontrollerisclockeddirectlyfromtheoutputofthesecondphase-lockedloop(PLL2)
ofthedevice.ThePLL2multipliesitsinputclockby20.Thisclockisdividedby2togenerateDDR_CLK.
ThefrequencyofDDR_CLKcanbedeterminedbyusingthefollowingformula:
DDR_CLKfrequency=(PLL2inputclockfrequency×20)/2=PLL2inputclockfrequency×10
ThesecondoutputclockoftheDDR2memorycontroller,DDR_CLK,istheinverseofDDR_CLK.For
moreinformationonthePLL2,seethedevice-specificdatamanual.
Pleaseseethedevice-specificdatamanualforinformationdescribingthedevicememorymap.
TheDDR2memorycontrollersignalsareshowninFigure2anddescribedinTable1.Thefollowing
featuresareincluded:
•Themaximumwidthforthedatabus(DDR_D[31:0])is32-bits.
•Theaddressbus(DDR_A[13:0])is14-bitswidewithanadditional3bankaddresspins(DDR_BA[2:0]).
•Twodifferentialoutputclocks(DDR_CLKandDDR_CLK)drivenbyinternalclocksources.
•Commandsignals:Rowandcolumnaddressstrobe(DDR_RASandDDR_CAS),writeenablestrobe
(DDR_WE),datastrobe(DDR_DQS[3:0]andDDR_DQS[3:0]),anddatamask(DDR_DQM[3:0]).
•Onechipselectsignal(DDR_CS)andoneclockenablesignal(DDR_CKE).
•Twoon-dieterminationoutputsignals(DDR_ODT[1:0]).
SPRUEK5A–October2007DSPDDR2MemoryController11
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