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CK
CK
CKE
CS
WE
RAS
CAS
LDM
UDM
LDQS
UDQS
BA[2:0]
A[12:0]
DQ[15:0]
VREF
DDR2
memory
x16−bit
LDQS
UDQS
DDR_CLK
DDR_CLK
DDR_CKE
DDR_CS
DDR_WE
DDR_RAS
DDR_DQM0
DDR_CAS
DDR_DQM1
DDR_DQS0
DDR_DQS0
DDR_DQS1
DDR_DQS1
DDR_BA[2:0]
DDR_A[13:0]
DDR_D[15:0]
DDR_DQM2
DDR_DQM3
DDR_DQS2
DDR_DQS3
DDR_D[31:16]
DDR_DQGATE0
(A)
DDR2
memory
controller
ODT
DDR_DQS2
DDR_DQS3
memory
x16−bit
LDQS
A[12:0]
VREF
ODT
DQ[15:0]
UDQS
BA[2:0]
UDQS
LDQS
LDM
UDM
RAS
CAS
WE
CS
CKE
CK
CK
DDR2
VREF
DDR_ODT0
DDR_ODT1
DDR_DQGATE1
(A)
DDR_DQGATE2
(A)
DDR_DQGATE3
(A)
UsingtheDDR2MemoryController
Figure17.ConnectingtoTwo16-BitDDR2SDRAMDevices
AThesepinsareusedasatimingreferenceduringmemoryreads.Forroutingrules,seethedevice-specificdata
manual.
30DSPDDR2MemoryControllerSPRUEK5A–October2007
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