Filter
Top Products
www.ti.com
2.11.2DDR2SDRAMInitializationAfterReset
2.11.3DDR2SDRAMInitializationAfterRegisterConfiguration
2.12InterruptSupport
2.13EDMAEventSupport
2.14EmulationConsiderations
PeripheralArchitecture
Table10.DDR2SDRAMExtendedModeRegister1Configuration(continued)
ModeModeRegister
RegisterBitFieldInitValueDescription
2ODTValue(Rtt)1On-dieterminationeffectiveresistance(Rtt)bits.Together
withbit2,thisbitselectsthevalueforRttas75Ω.
1OutputDriverSDCFG.DDR_DRIVEOutputdriverimpedancecontrolbits.Initializedusingthe
ImpedanceDDR_DRIVEbitoftheSDRAMconfigurationregister
(SDCFG).
0DLLEnable0DLLenable/disablebits.DLLisalwaysenabled.
Afterahardorasoftreset,theDDR2memorycontrollerwillautomaticallystarttheinitializationsequence.
TheDDR2memorycontrollerwillusethedefaultvaluesintheSDRAMtiming1andtiming2registersand
theSDRAMconfigurationregistertoconfigurethemoderegistersoftheDDR2SDRAMdevice(s).Note
thatsinceasoftresetdoesnotresettheDDR2memorycontrollerregisters,aninitializationsequence
startedbyasoftresetwouldusetheregistervaluesfromapreviousconfiguration.
Theinitializationsequencecanalsobeinitiatedbyperformingawritetothetwoleast-significantbytesin
theSDRAMconfigurationregister(SDCFG).Usingthisapproach,dataandcommandsstoredinthe
DDR2memorycontrollerFIFOsarenotlostandtheDDR2memorycontrollerensuresreadandwrite
commandsarecompletedbeforestartingtheinitializationsequence.
Performthefollowingstepstostarttheinitializationsequence:
1.SettheBOOT_UNLOCKbitintheSDRAMconfigurationregister(SDCFG).
2.Writea0totheBOOT_UNLOCKbitalongwiththedesiredvaluefortheDDR_DRIVEbit.
3.ProgramtherestoftheSDCFGtothedesiredvaluewiththeTIMUNLOCKbitset(unlocked).
4.ProgramtheSDRAMtiming1register(SDTIM1)andSDRAMtimingregister2(SDTIM2)withthe
valueneededtomeettheDDR2SDRAMdevicetimings.
5.ProgramtheREFRESH_RATEbitsintheSDRAMrefreshcontrolregister(SDRFC)toavaluethat
meetstherefreshrequirementsoftheDDR2SDRAMdevice.
6.ProgramSDCFGwiththedesiredvalueandtheTIMUNLOCKbitcleared(locked).
7.Programthereadlatency(RL)bitintheDDR2memorycontrollercontrolregister(DMCCTL)tothe
desiredvalue.
TheDDR2memorycontrollerdoesnotgenerateanyinterrupts.
TheDDR2memorycontrollerisaDMAslaveperipheralandthereforedoesnotgenerateEDMAevents.
DatareadandwriterequestsmaybemadedirectlybymastersincludingtheEDMAcontroller.
TheDDR2memorycontrollerwillremainfullyfunctionalduringemulationhaltstoallowemulationaccess
toexternalmemory.
DSPDDR2MemoryController 28SPRUEK5A–October2007
SubmitDocumentationFeedback