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3.2.3ConfiguringSDRAMTimingRegisters(SDTIM1andSDTIM2)
UsingtheDDR2MemoryController
Table12displaystheDDR2-533refreshratespecification.
Table12.DDR2MemoryRefreshSpecification
SymbolDescriptionValue
t
REF
AveragePeriodicRefreshInterval7.8μs
Therefore,thevaluefortheREFRESH-RATEcanbecalculatedasfollows:
REFRESH_RATE=266.5MHz×7.8μs=2078.7=81Eh
Table13showstheresultingSDRFCconfiguration.
Table13.SDRFCConfiguration
FieldValueFunctionSelection
SR0DDR2memorycontrollerisnotinself-refreshmode.
REFRESH_RATE81EhSetto81EhDDR2clockcyclestomeettheDDR2memoryrefreshrate
requirement.
TheSDRAMtiming1register(SDTIM1)andSDRAMtiming2register(SDTIM2)configuretheDDR2
memorycontrollertomeetthedatasheettimingparametersoftheattachedDDR2device.Eachfieldin
SDTIM1andSDTIM2correspondstoatimingparameterintheDDR2datasheetspecification.Table14
andTable15displaytheregisterfieldnameandcorrespondingDDR2datasheetparameternamealong
withthedatasheetvalue.Thesetablesalsoprovideaformulatocalculatetheregisterfieldvalueand
displaystheresultingcalculation.Eachoftheequationsincludeaminus1becausetheregisterfieldsare
definedintermsofDDR2clockcyclesminus1.SeeSection4.5andSection4.6formoreinformation.
Table14.SDTIM1Configuration
DDR2SDRAM
DataSheet
RegisterParameterDataSheetFormula(RegisterFieldField
FieldNameNameDescriptionValue(nS)MustBe≥)Value
T_RFCt
RFC
Refreshcycletime127.5(t
RFC
×f
DDR2_CLK
)-133
T_RPt
RP
Prechargecommandtorefreshor15(t
RP
×f
DDR2_CLK
)-13
activatecommand
T_RCDt
RCD
Activatecommandtoread/write15(t
RCD
×f
DDR2_CLK
)-13
command
T_WRt
WR
Writerecoverytime15(t
WR
×f
DDR2_CLK
)-13
T_RASt
RAS
Activetoprechargecommand40(t
RAC
×f
DDR2_CLK
)-110
T_RCt
RC
ActivatetoActivatecommandinthe55(t
RC
×f
DDR2_CLK
)-114
samebank
T_RRDt
RRD
ActivatetoActivatecommandina10(t
RRD
×f
DDR2_CLK
)-13
differentbank
T_WTRt
WTR
Writetoreadcommanddelay7.5(t
WTR
×f
DDR2_CLK
)-11
DSPDDR2MemoryController 34SPRUEK5A–October2007
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