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3.2.4ConfiguringtheDDR2MemoryControllerControlRegister(DMCCTL)
UsingtheDDR2MemoryController
Table15.SDTIM2Configuration
DDR2SDRAMData
RegisterFieldSheetParameterDataSheetFormula(RegisterField
NameNameDescriptionValueFieldMustBe≥)Value
T_ODTt
AOND
t
AOND
specifiestheODT2(t
CK
cycles)CASlatency-t
AOND
-11
turn-ondelay
T_SXNRt
SXNR
Exitselfrefreshtoanon-read137.5nS(t
SXNR
×f
DDR2_CLK
)-136
command
T_SXRDt
SXRD
Exitselfrefreshtoaread200(t
CK
cycles)(t
SXRD
)-1199
command
T_RTPt
RTP
Readtoprechargecommand7.5nS(t
RTP
×f
DDR2_CLK
)-11
delay
T_CKEt
CKE
CKEminimumpulsewidth3(t
CK
cycles)(t
CKE
)-12
TheDDR2memorycontrollercontrolregister(DMCCTL)containsareadlatency(RL)fieldthathelpsthe
DDR2memorycontrollerdeterminewhentosamplereaddata.TheRLfieldshouldbeprogrammedtoa
valueequaltoCASlatencyplus1.Forexample,ifaCASlatencyof4isused,thenRLshouldbe
programmedto5.
Table16.DMCCTLConfiguration
Register
RegisterFieldNameDescriptionValue
IFRESETProgrammedtobeoutofreset.0
RLReadlatencyisequaltoCASlatencyplus1.5
SPRUEK5A–October2007DSPDDR2MemoryController35
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