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1DDR2MemoryControllerSignalDescriptions.........................................................................12
2DDR2SDRAMCommands...............................................................................................13
3TruthTableforDDR2SDRAMCommands............................................................................13
4AddressableMemoryRanges............................................................................................18
5BankConfigurationRegisterFieldsforAddressMapping............................................................19
6DDR2MemoryControllerFIFODescription............................................................................22
7RefreshUrgencyLevels...................................................................................................25
8ResetSources..............................................................................................................26
9DDR2SDRAMModeRegisterConfiguration...........................................................................27
10DDR2SDRAMExtendedModeRegister1Configuration............................................................27
11SDCFGConfiguration.....................................................................................................33
12DDR2MemoryRefreshSpecification...................................................................................34
13SDRFCConfiguration......................................................................................................34
14SDTIM1Configuration.....................................................................................................34
15SDTIM2Configuration.....................................................................................................35
16DMCCTLConfiguration....................................................................................................35
17DDR2MemoryControllerRegisters.....................................................................................36
18ModuleIDandRevisionRegister(MIDR)FieldDescriptions........................................................37
19DDR2MemoryControllerStatusRegister(DMCSTAT)FieldDescriptions........................................37
20SDRAMConfigurationRegister(SDCFG)FieldDescriptions........................................................38
21SDRAMRefreshControlRegister(SDRFC)FieldDescriptions.....................................................40
22SDRAMTiming1Register(SDTIM1)FieldDescriptions.............................................................41
23SDRAMTiming2Register(SDTIM2)FieldDescriptions.............................................................43
24BurstPriorityRegister(BPRIO)FieldDescriptions....................................................................44
25DDR2MemoryControllerControlRegister(DMCCTL)FieldDescriptions.........................................45
A-1DocumentRevisionHistory...............................................................................................46
SPRUEK5A–October2007ListofTables5
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